The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 1989
Filed:
Apr. 17, 1987
John E Davey, Alexandria, VA (US);
The United States of America as represented by the Secretary of the Navy, Washington, DC (US);
Abstract
A self-aligned GaAs FET with an active channel which is unaffected by sure charge trapping/emission. The device comprises a channel of n-doped GaAs, a source and drain regions of n.sup.+ GaAs disposed at opposite ends of the channel, a semi-insulating GaAs layer disposed over the channel, with this GaAs layer having open first and second end surfaces disposed at an angle of greater than or equal to 45.degree. relative to the channel plane. A cavity is disposed in the GaAs layer exposing a portion of the channel, and a gate metallization is disposed over the GaAs layer and extending from the first end surface to the second end surface of the GaAs layer and directly contacting the exposed portion of the channel region in the cavity to form a Schottky barrier contact. This gate metallization is not disposed in contact with a significant portion of either of the first and second end surfaces. The ends of the gate metallization overhang slightly the end surfaces of the GaAs layer in order to provide masking to maintain the first and second end surfaces open during fabrication. An insulator such as air may be disposed in contact with these end surfaces.