The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 1989
Filed:
Jun. 01, 1988
Tatsuya Deguchi, Kawasaki, JP;
Fumitake Mieno, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
The present invention is a method for fabricating bipolar-MOS devices having n-MOSs, p-MOSs and bipolar transistors, each fabricated in a respective silicon single crystal layer grown in openings formed in a field oxide layer covering a silicon substrate. Over the field oxide layer, having openings where the active devices should be fabricated, is applied an epitaxial growth of silicon. By this operation, single crystal layers are formed in the openings, and a polysilicon layer is formed on the field oxide layer. The polysilicon layer is patterned to form the source and drain contact electrodes of the FETs and the base and collector contact electrodes of the bipolar transistors simultaneously. To the active areas, contact electrodes for the p-MOS, and base contact electrodes of the npn bipolar transistors are simultaneously implanted with p type impurities by ion implantation. The active areas, contact electrodes for the n-MOS, and the collector contact electrodes of the npn bipolar transistors are simultaneously implanted with n type impurities by ion implantation. For the pnp transistors, an inverse process of the above is applied. By such a method, the process for fabricating the bipolar-MOS device is simplified, and the operation of the device is improved.