Variable delay circuit for delaying input data

Abstract

A bit length corresponding to a delay time of required data is preset in a bit length setting circuit (15). A write timing signal from an external control circuit (6) is applied to a write address decoder (3) and a read timing signal generating circuit (2). Input data is written into memory cells in a memory device (5) addressed by the write address decoder (3) operating in response to the write timing signal. On the other hand, a read timing signal generating circuit (2) generates a read timing signal delayed from the write timing signal by a delay time corresponding to a bit length signal in response to the bit length signal from the bit length setting circuit (15) and the write timing signal from outside. The read address decoder (4) sequentially addresses memory cells containing input data which have been written, reads written data and then outputs output data. Applications of the circuit include frame synchronization, variable delay and storage of picture data in a video communications system.