The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1989

Filed:

Aug. 25, 1988
Applicant:
Inventor:

Toshitaka Fukushima, Yokohama, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 67 ; 437 61 ; 437228 ; 437235 ;
Abstract

In manufacturing processes of an integrated circuit, isolation technology between adjacent active elements on a substrate plays an important role. Groove isolation filled with dielectric is known as an effective way of achieving a high integration density, however the prior art methods of forming the isolation groove have the problem of formation of BIRD'S HEAD or BIRD'S BEAK portions around the isolation region, which restricts the integration density and deteriorates a flatness of the substrate. The method of forming isolation groove according to the present invention discloses that the method comprising the steps of removing a silicon oxide layer on a specified region surrounding the isolation groove, and depositing a silicon nitride layer directly on the substrate and forming the groove self-aligned using the above silicon oxide layer removal process, eliminates the above mentioned problems achieving a higher density of integration, a flatness of the substrate and improvement of the integrated circuit.


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