The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 1989
Filed:
Dec. 11, 1985
Eric J Wildi, Clifton Park, NY (US);
Tat-Sing P Chow, Schenectady, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A semiconductor wafer having a substrate with an epitaxial layer thereon includes a semiconductor device electrically isolated from the substrate as well as from any other devices in the wafer by electrical isolation structure comprising semiconductor material. The semiconductor device can accordingly be operated at high voltage with respect to the wafer substrate. The isolation structure in one form of the wafer comprises an N+ high voltage tub included in the wafer and a P+ ground region situated in the expitaxial layer, adjoining the substrate, and horizontally circumscribing the N+ high voltage tub and being spaced therefrom by a minimum layer extent of a portion of the epitaxial layer that is of N conductivity type. The N+ high voltage tub comprises an N+ high voltage region situated in the epitaxial layer and surrounding a device region in which the semiconductor device is at least partially contained and, further, an N+ buried layer underlying the N+ high voltage region and the entirety of the device region.