Programmable data security circuit for programmable logic device

Abstract

An architecture security fuse circuit is disclosed for securing the architecture of a configurable programmable logic device. The storage element of the circuit is a floating gate transistor cell. Data stored in the cell is determined by the amount of charge trapped within the oxide-isolated polysilicon floating gate region. The security fuse is initialized (erased) during device fabrication to allow access to device architectural data. Such initialization is accomplished by a technique that the device user cannot duplicate, via an extra probe pad accessible only during wafer probe. To deter the effects of floating gate charge loss which may occur during subsequent fabrication steps, the fuse circuit is adapted to provide a reduced memory cell read voltage, thus providing greater margin against thermally defeating the security fuse. A regenerative feature is provided to strengthen the erased cell during every device 'clear' cycle. Once the security fuse is programmed, the data defining the device architecture may not be interrogated or altered, and the memory cell is unchanged by the regenerative feature.