Self-aligned gate fet process using undercut etch mask

Abstract

The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.