The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 1989

Filed:

Mar. 08, 1988
Applicant:
Inventors:

James R Pfiester, Austin, TX (US);

John R Yeargain, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 24 ; 437 27 ; 437 29 ; 437 41 ; 437200 ; 437933 ; 357 231 ;
Abstract

A salicided twin-tub CMOS process using germanium implantation to retard the diffusion of the dopants, such as phosphorus and boron. Implantation of n+ and p+ dopants after titanium salicidation is employed to fabricate devices with low junction leakage and good short-channel effects. Also, the germanium dopant may be introduced before or after the formation of the refractory metal silicide formation, and may be implanted independently or together with the dopant whose diffusion in the silicon it will modify. The employment of germanium permits the use of a phosphorus implant through a relatively thick refractory metal silicide contact layer. If arsenic is implanted through the silicide layer to solve the deep junction problem, the silicide layer must be thin to permit the passage of the larger arsenic atoms typically stopped by the silicide. Thinner silicide layers have the disadvantage of higher sheet resistances.


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