Planar famos transistor with sealed floating gate and dcs+n.sub.2 o oxide

Abstract

The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.