The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 1989

Filed:

Apr. 08, 1988
Applicant:
Inventors:

William T Cochran, New Tripoli, PA (US);

Agustin M Garcia, Allentown, PA (US);

Graham W Hills, Allentown, PA (US);

Jenn L Yeh, Macungie, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C / ; C23F / ; C03C / ; C03C / ;
U.S. Cl.
CPC ...
156644 ; 156653 ; 156656 ; 156657 ; 1566591 ; 357 71 ; 437203 ; 437228 ;
Abstract

A self-assigned, self-planarized metallization scheme for multilevel interconnections using self-aligned windows in integrated circuits is described. Trenches are etched into a dielectric and then, using an etch stop layer on top of the dielectric to prevent unwanted etching of the dielectric, self-aligned windows which expose portions of the substrate are etched in the dielectric. Self-aligned windows can also be formed without a mask.


Find Patent Forward Citations

Cochran, William. (1989). Semiconductor devices having multi-level metal interconnects (U.S. Patent No. 4832789). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4832789

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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