Self-aligned channel stop

Abstract

Disclosed is a process of forming channel stops which starts with a, for example, N type silicon substrate having on the surface thereof an insulator trench mask defining the region of silicon where an isolation trench is desired. A blockout layer having an opening in correspondence with the portion of the would-be silicon mesa where a channel stop is desired is formed. N type dopant is introduced into the exposed silicon followed by an anneal step to and vertically diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region. Upon forming a pair of highly P doped regions on either side of the shallow highly N doped region, the latter functions as a channel stop to arrest charge leakage between the P doped regions due to parasitic FET action at the trench walls.