The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 1989
Filed:
Sep. 03, 1987
Applicant:
Inventors:
Andrew M Volk, Loomis, CA (US);
Terry L Baucom, Citrus Heights, CA (US);
Roger Van Brunt, San Francisco, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
328134 ; 328133 ; 328155 ; 331 / ; 375119 ;
Abstract
An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.