Technique for forming planarized gate structure

Abstract

A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.