The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 1989

Filed:

May. 06, 1988
Applicant:
Inventors:

Carlos L Barton, Brooklyn, CT (US);

Adrienne Lindsay, Chandler, AZ (US);

Samuel W Henson, Mesa, AZ (US);

Assignee:

Rogers Corporation, Rogers, CT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C25D / ; C25D / ;
U.S. Cl.
CPC ...
204 15 ; 204 384 ;
Abstract

A multilayer through-hole contacted flexible circuit and method of manufacture thereof is presented having a laminar construction which is strictly symmetrical in the bending area; and which has no exposed adhesive. The flexible circuit is made by providing through-holes to a standard single sided laminate. Next, conductive material is vacuum deposited (e.g. sputtered or evaporated) into the through-holes and at the same time a conductive seed-layer is deposited on the polymer side of the standard laminate. Plating resist is applied to both sides of the material and the seed-layer side of the material is patterned such that circuit traces, pads, and through-holes can be electroplated with additional copper. The plating resist is stripped and the very thin layer of copper in the non-conductive areas is flash etched to produce semi-additive circuit features on the seed-layer side. Etch resist is then applied to both sides of the material and circuit patterns fabricated on the foil-side of the material using standard substractive processing techniques. A cover film coated with adhesive is then provided over the exposed circuit patterns.


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Barton, Carlos. (1989). Process for the manufacture of multi-layer circuits with dynamic flexing (U.S. Patent No. 4812213). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4812213

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