The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 1989
Filed:
Jun. 24, 1987
Rathindra N Putatunda, Marlton, NJ (US);
David C Smith, Williamstown, NJ (US);
Stephen A McNeary, Somerville, NJ (US);
General Electric Company, Moorestown, NJ (US);
Abstract
An automated LSI chip layout arrangement includes automated layout of the power bus distribution network. A complete interlocking mesh of buses is run in routing channels lying between groups of circuits to be powered. Each segment of the mesh powering net which affects the chip size is tested to see if it can be removed without adversely affecting the power distribution. If it can be removed, the segment is deleted. The next segment which is critical to the size of the chip is then tested, and the process is continued. Those segments of the power bus distribution network which do not affect the size of the chip are not eliminated. Thus, a low-resistance power distribution bus network is guaranteed, and chip size is minimized.