The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 1989
Filed:
Jan. 22, 1987
Applicant:
Inventor:
Kirby S Hallenbeck, Shingle Springs, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
365 94 ; 365189 ; 365185 ; 365104 ; 307554 ;
Abstract
A latch circuit provides for a reading of a state of an EPROM cell and retains that state after the reading sequence is completed. The memory state of the EPROM is inputted to a NOR gate during a power on reset condition. The output of the NOR gate is fed back through an inverter to the input of the NOR gate, such that when the EPROM is deactivated, the input of the NOR gate is latched to the previous EPROM memory state.
Hallenbeck, Kirby. (1989). Eprom latch circuit (U.S. Patent No. 4803659). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4803659
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile