The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 1989
Filed:
Apr. 02, 1987
Franz Neppl, Munich, DE;
Carlos-Alberto Mazure-Espejo, Kirchseeon, DE;
Siemens Aktiengesellschaft, Berlin and Munich, DE;
Abstract
A method for the manufacture of neighboring wells 9, implanted with dopant ions of differing conductivity type in silicon substrates provided with an epitaxial layer. A lateral under-etching having high selectivity to specified layers is designationally introduced into a silicon nitride layer provided for masking the n-well regions in the implantation of the p-wells. Thus, the edge of a silicon oxide layer serving as a masking in the following oxidation shifts in the direction of the n-wells. As a result of this type of self-adjusted well production, the influence of the counter-doping in the region of the well boundaries is noticeably reduced. In addition, a polysilicon layer can also be employed under the silicon nitride layer as a masking layer, this layer eing co-oxidized after the under-etching of the silicon nitride layer. Thus a box-shaped course is produced in the masking oxide instead of the prior art bird's bill course, whereby a steeper diffusion front is achieved in the n-well. The method serves for the manufacture of VLS1 complementary MOS field effect transistor circuits.