The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 1989

Filed:

Feb. 04, 1988
Applicant:
Inventors:

Jun-ichi Okano, Hyogo, JP;

Kiyohito Matsumoto, Himeji, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 51 ; 437162 ; 437911 ; 357 22 ;
Abstract

A method for manufacturing cascaded junction type field effect transistors comprises the steps of forming an epitaxial layer of a first conductivity type used as a channel region on a semiconductor substrate of a second conductivity type and performing selective oxidation to form a thick oxide film on part of the epitaxial layer. Then, the thick oxide film is removed to provide a part of the surface which is a level lower than the main surface of the epitaxial layer. Next, an impurity of the first conductivity type is doped into the low and high surface areas of the epitaxial layer from the surface thereof to form source and drain regions separated at a preset distance. After this, an impurity of the second conductivity type is doped into the low and high level surface areas of the epitaxial layer between the source and drain regions to simultaneously form first and second junction gates which are separated at a present distance. Then, the semiconductor substrate is connected to the second junction gate and source region to connect two junction FETs in cascade fashion.


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