The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 1989
Filed:
Jun. 02, 1987
Mitsugi Ogura, Yokohama, JP;
Fujio Masuoka, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that atea of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer. A MOS transistor is formed in the surface portion of the second conductive layer.