The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 1989
Filed:
Nov. 03, 1987
William S Phy, Los Altos Hills, CA (US);
Fairchild Camera and Instrument Corporation, Mountain View, CA (US);
Abstract
A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads on the chip package, the lead alignment bars being formed from a material providing electrical isolation between leads during testing of the chip package and for providing physical spacing between the leads both during testing and later mounting of the chip package on the substrate so as to prevent adjacent leads from inadvertent contact. Preferably, the lead alignment bars are formed from a high resistivity material selected to provide sufficient conductivity between the interconnected leads for minimizing electrostatic discharge conditions therebetween, the material being sufficiently non-conductive to permit functional and dynamic testing of the leads. After testing of the chip package, it is mounted on the substrate with the interconnecting lead alignment bars then being removed to facilitate subsequent operation of the chip package.