Selective backside plating of gaas monolithic microwave integrated

Abstract

A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.