The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 1988
Filed:
Nov. 24, 1986
Toshitaka Fukushima, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents minority carries in each of the paired bases from diffusing into an adjacent base, and thus, prevents influence between the paired memory cells. The base contact region may be isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block composed of the paired cells and the base contact region is isolated at its circumference by the narrow groove. The narrow isolation grooves and the elimination of a conventional buried base layer reduce stray capacitance and increase the current amplification factors of the transistors. In addition, less current is required, thus increasing the switching speed, lowering power comsumption, and reducing the occupation area for memory cells and the peripheral circuit, resulting in increased integration density.