The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 1988
Filed:
Oct. 23, 1986
Charles C Austin, El Toro, CA (US);
Silicon Systems, Inc., Tustin, CA (US);
Abstract
A TTL/CMOS interface circuit comprised entirely of CMOS components. An input gain stage comprised of transistors of a single conductivity type is provided whose gain is established by the ratio of the geometric size of the transistors. In the preferred embodiment of the present invention, the input gain stage is comprised of N channel transistors to a void process related mismatches. An inverter stage has a switching threshold set to optimally operate with the output of the input gain stage. The voltage at the inverter stage is tied to the power supply voltage to supply an upper voltage limit. In order to provide for zero power operation for input signals close the value of the supply voltage, a transistor is provided to cut current flow in the input stage for input signals within a threshold voltage of the supply voltage. The present circuit may also be utilized as to allow zero power operation for input signals close to ground.