The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 1988
Filed:
Jun. 01, 1987
David J Reed, Mesa, AZ (US);
Robert K Fairbanks, Phoenix, AZ (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A coplanar die to substrate bond method wherein a plurality of die are aligned on a silicon wafer substrate in a predetermined relationship and a slurry of glass is applied to bond them together. This occurs while either on a flat or a grooved plate. When the silicon wafer substrate and the plurality of die are ready for firing, they are placed on a grooved plate so that grooves are below the glass thereby decreasing the capillary force which commonly causes overflow. With reduced overflow, the bonding can be done at a higher temperature to reduce underflow. Because there is no underflow or overflow using this process, a greater degree of coplanarity is achieved thereby making future processing steps, such as the processing of interconnect lines, much easier to perform.