The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 1988

Filed:

Jun. 17, 1986
Applicant:
Inventors:

Harlan Lawler, Milpitas, CA (US);

William S Phy, Los Altos Hills, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 71 ; 228121 ; 228123 ; 228124 ;
Abstract

A process for bonding silicon die to a package. This process comprises the following steps: (a) providing to the back surface of the die an adhesion layer of material which exhibits superior adhesion to both the silicon die and a subsequently applied barrier layer; (b) providing to the adhesion layer a barrier layer which is impervious to silicon; (c) providing to the barrier layer a bonding layer; and (d) bonding the die to the package by activating a binder composition disposed at the interface of the package and the bonding layer. The barrier layer prevents the migration of silicon to the bonding layer, both at the time of application of the bonding layer to the die and at the time of bonding the die to the package. The adhesion layer enhances the adhesion of the barrier layer material to the back surface of the die. Titanium is the preferred adhesion layer material while tungsten is the preferred barrier layer material. The bonding layer preferably comprises gold while the preferred binder composition is a gold-tin alloy solder. The enhanced adhesion of the barrier layer which prevents silicon migration into the gold produces highly reliable bonds. In another embodiment, a stress relief layer is interposed between the adhesion layer and the back of the silicon die. The material of the stress relief layer is alloyed to the silicon at the back surface of the die which relieves stresses in the die and enhances the planarity of the back surface. This produces bonds which exhibit superior electrical and thermal contact characteristics.


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