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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4771286 B1

PDFFull Text
Date of Patent:
Sep. 13, 1988

Filed:

Jul. 28, 1986

Lan controller having split bus design

Applicant:
Inventors:

Leonard E Niessen, Framingham, MA (US);

Allen C Hirtle, Littleton, MA (US);

Edward Beauchemin, Marlboro, MA (US);

Assignee:

Honeywell Bull Inc., Minneapolis, MN (US);

Attorneys:

Prasinos; Nicholas

Solakian; John S.

Grayson; George

Primary Examiner:

Donald J Yusko

Int. Cl.
CPC ...
H04Q / ; H04J / ;
U.S. Cl.
CPC ...
340825520 ; 370 85 ;
Abstract

A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (.mu.P) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

Find Patent Forward Citations

Niessen, Leonard. (1988). Lan controller having split bus design (U.S. Patent No. 4771286). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4771286

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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