Method and structure for a high density vmos dynamic ram array

Abstract

A vertical DRAM cell using VMOS transistors and trench capacitors and the fabrication process therefor. A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination is provided wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate connected to a word line, its drain connected to a bit line, and its source connected to a storage capacitor. More particularly, the storage capacitance node is connected to the source of the V-groove access device through a conducting bridge. The gate of the V-groove access device is connected to the polysilicon word line and the drain is a diffused region which also serves as the bit line of the cell. An epitaxial layer is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.