Two mask technique for planarized trench oxide isolation of integrated

Abstract

A two mask process for forming dielectrically filled planarized trenches of arbitrary width in a semiconductor substrate, the masks being of such character that they are amenable to computerized generation. The first mask defines the active regions and subdivides the trench isolation regions into a succession of trench and plateau regions, where the widths of the trench and plateau regions fall within in a dimensional range constrained by photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask in place, the semiconductor is anisotropically etched to formed the first trench regions. A conformal deposition of dielectric follows, and by virtue of the dimensional constraints ensures substantially void free trench dielectric and a concluding substantially planar topology of the dielectric on the substrate surface. Following the etch of the deposited dielectric to the level of the plateau and active region surfaces, a second mask, defined to be slightly larger than the active regions, is formed over the substrate. A selective etch is then applied to remove the plateau regions and thereby form new trenches approximating in depth the first trenches. A second conformal deposition of dielectric follows, to fill the plateau region defined trenches in the manner of the first dielectric deposition. An etch of the second dielectric to the surface of the active regions follows to complete the fabrication. The substrate surface is planar and now divided into active regions which are separated by oxide filled, arbitrary width trenches.