The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 1988
Filed:
Aug. 11, 1986
Hiroshi Asazawa, Tokyo, JP;
Kazuya Hashimoto, Tokyo, JP;
NEC Corporation, , JP;
Abstract
A bias circuit for an FET comprises a voltage divider having two potential points. A first of the potential points is connected to a gate of the FET. The other potential point is connected through a second FET which may be turned off or on to vary the potential at the first potential point in order to control the bias on the gate of the first FET. The switching of the second FET is controlled as a function of a threshold voltage between its gate and a voltage in the source-drain circuit of the second FET. In one embodiment, a diode feedback circuit may be used to provide the threshold current.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile