Method for improving wirability of master-image dcvs chips

Abstract

A method for increasing the wirability of complementary metal oxide semiconductor (CMOS) differential cascode voltage switch (DCVS) logic circuits which comprises designing the circuitry to permit as many of the internal tree connections as possible to be wired using diffusion techniques. The method utilizes differential pair and load microblocks which have been designed so as to allow mirroring on a vertical center line. Utilizing the availability of mirroring for individual pairs plus relocation of individual pairs in the logic tree the crossings may be largely eliminated in a shortened period. It utilizes a step by step row and column analysis of the initial or starting tree design resulting from the basic Boolean logic to be performed by the particular circuit and makes required load mirroring and differential pair relocation decisions in an iterative process. The transistor pairs and load devices may be mirrored about a vertical center line. That is, they have an alternate configuration or layout in which left and right are reversed. The effect of mirroring is to reverse the points of connection for the true and complement inputs to the load, and to reverse the true and complement output locations of the pairs, WITHOUT switching the horizontal wiring tracks occupied by the inputs to the pairs, or outputs from the loads.