The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 1988
Filed:
Oct. 21, 1985
Applicant:
Inventors:
Randall M Chung, Laguna Niguel, CA (US);
Bradley S Masters, Chino, CA (US);
Assignee:
Western Digital Corporation, Irvine, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307468 ; 307443 ; 307452 ; 307469 ; 307481 ; 34082583 ; 364716 ;
Abstract
Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a clock signal and its complement and are separated by a clocked latch/inverter for providing correct logic evaluation between the logic planes.