The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 1988

Filed:

Aug. 28, 1986
Applicant:
Inventor:

Hidemi Ishiuchi, Fujisawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 48 ; 427 52 ; 437 52 ;
Abstract

A method of manufacturing a MOS semiconductor device which comprises a first step of forming a p-type well region in the surface of an n-type silicon substrate, a second step of forming a field oxide layer surrounding part of the surface of the well region, a third step of ion-implanting a n-type impurity into the surface of the well region, to reduce the carrier density of the well region in the vicinity of the ion-implanted without changing the conductivity type of the well region, a fourth step of forming a gate electrode insulatively on the ion-implanted surface of the well region, and a fifth step of forming the n.sup.+ -type source and drain regions in the ion-implanted surface of the well region. The third step of this manufacturing method uses the field oxide layer for implanting the n-type impurity, as a mask.


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