The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 1988
Filed:
May. 16, 1986
William G Wilke, Arlington, MA (US);
Tektronix, Inc., Beaverton, OR (US);
Abstract
An electronic circuit for selectively generating two output pulses that differ in duration by a predetermined amount has a clock terminal for receiving clock transitions at precisely determined intervals and comprises first and second sequential logic devices, a combinational logic device and a network that couples the clock terminal of the circuit to the sequential logic devices and also couples the second sequential logic device to the combinational logic device. The first and second sequential logic devices each have a data input terminal, a clock input terminal and an output terminal, and each has a first state in which the output terminal is at one of two binary logic levels and a second state in which the output terminal is at the other of the two binary logic levels. The combinational logic device has a first input terminal coupled to the output terminal of the first sequential logic device, a second input terminal coupled to the output terminal of the second sequential logic device, and an output terminal at which the desired two output pulses are provided. The coupling network has first and second separately selectable states such that in the first state of the coupling network a change in the state of the first sequential logic device brings about a change in the state of the second sequential logic device after a first predetermined number of clock transitions, whereas in the second state of the coupling network a change in the state of the first sequential logic device brings about a change in the state of the second sequential logic device after a second predetermined number of clock transitions, the second number being different from the first number.