The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 1988
Filed:
Oct. 15, 1985
Jeffrey K Kaszubinski, Houston, TX (US);
Debra J Dolby, Missouri City, TX (US);
Timmie M Coffman, Sugar Land, TX (US);
John F Schreck, Houston, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transistor and a ground select transistor coupled to each of the drain and source lines. Each selected floating gate transistor in a programming mode is in series with control and ground select transistors between a high voltage Vpp and ground potential. A resistive element in series with a first conducting circuit element establishes a reference current which generates a voltage V.sub.1 at the junction of the resistive element and the circuit element. In a second current leg a second conducting circuit element, a module floating gate transistor biased into a conducting state and a module control transistor are all connected between Vpp and ground such that a voltage V.sub.2 is established at the junction of the second circuit element and the module floating gate transistor. Comparing means compares voltages V.sub.1 and V.sub.2 and adjusts the gate voltage V.sub.3 of the module programming control transistor so as to make the voltage V.sub.2 equal to voltage V.sub.1 and applies voltage V.sub.3 to the gates of the array programming control transistors. Since the transistor in the reference path is both electrically and geometrically the same as that in the second leg across which the voltage developed is compared, and is made by the same process, the current in the second leg will be substantially the same as that in the reference leg. Moreover, since the array floating gate transistors are also made by the same process as is the module floating gate transistor and the programming control and ground select transistors are also identical, by feeding the voltage V.sub.3 to array control transistors substantially the same current will flow through a selected array transistor as flows through both the reference current path and the second current leg.