The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 1988
Filed:
Sep. 19, 1986
Calvin D Diller, Hillsboro, OR (US);
Donald D Gladden, Portland, OR (US);
Tektronix, Inc., Beaverton, OR (US);
Abstract
A level shift circuit for shifting the common mode level of the output signal provided by a differential amplifier has first and second input terminals for receiving the output signal from the differential amplifier, which has a Thevenin source impedance R.sub.s, and also has first and second output terminals that are connected to a reference voltage level through a load impedance R.sub.o. The circuit comprises a differential transconductance amplifier having two output terminals that are connected respectively to the first and second output terminals of the circuit. The amplifier has the property that it responds to an input voltage E.sub.e between its input terminals by providing a current equal to E.sub.e g.sub.ml /(1+.tau.s) (where g.sub.ml is the transconductance of the amplifier, .tau. is the response time constant of the amplifier and s is the Laplace transform operator) at its output terminals. Two equal-valued capacitors are connected respectively between the first input terminal of the circuit and the first output terminal of the circuit and between the second input terminal of the circuit and the second output terminal of the circuit, the capacitance C.sub.c of each capacitor being such that R.sub.s C.sub.c is much greater than .tau.. The circuit also comprises two equal-valued resistors connected in series between the first input terminal of the circuit and the second output terminal of the circuit and having their connection point connected to one of the input terminals of the amplifier, and two more equal-valued resistors connected in series between the first output terminal of the circuit and the second input terminal of the circuit and having their connection point connected to the other of the two input terminals of the amplifier. The value of g.sub.ml is selected to be equal to (1/2R.sub.s +1/R).