The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 1987

Filed:

Nov. 28, 1984
Applicant:
Inventors:

Takeshi Okazawa, Tokyo, JP;

Yoshiyuki Hirano, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437200 ; 437193 ; 437 41 ; 437983 ;
Abstract

A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film and the surface of the metal silicide film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no short-circuiting is necessary. For example, in an insulated gate field effect transistor, the gate electrode is constituted by the polycrystalline silicon layer and the metal silicide film at the side walls of the polycrystalline silicon layer. Such a gate electrode has a low electrical resistance and does not cause undesirable short-circuiting with source and drain regions by the existence of the silicon oxide film formed on the surface of the metal silicide film. Also, other metal silicide film may be formed on the upper surface of the gate electrode. Moreover the silicide-SiO.sub.2 structure may be used on the source and drain regions.


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