The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 1987
Filed:
Sep. 29, 1986
Applicant:
Inventors:
Hong-Kyun Choi, Concord, MA (US);
Bor-Yeu Tsaur, Bedford, MA (US);
Assignee:
Massachusetts Institute of Technology, Cambridge, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 41 ; 437238 ; 437 83 ;
Abstract
A self-aligned integrated JFET device is described wherein an oxide extension region and a doped polysilicon gate is used as part of a self-aligned mask to form drain and source regions. Asymmetric JFETs for power circuit applications can be made in accordance with the invention. Additionally, complementary enhancement mode JFETs can be made in accordance with the invention, for low power consumption and excellent radiation-hardened characteristics.
Choi, Hong-Kyun. (1987). Process for making junction field-effect transistors (U.S. Patent No. 4700461). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4700461
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile