The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 1987
Filed:
Jul. 10, 1986
Michael T Imel, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed. The memory is driven by a clock such that during particular clock phase a ROW line (50) and a MATCH line (52) are precharged and both column lines are discharged. The memory cell is comprised of transistors (M1, M2, M3, M4) connected to each other and to a supply voltage (Vcc) to thereby form a cross-coupled inverter storage device. Transistors (M5, M6) are connected to diode transistor (M7) and between the cross-coupled inverter (M1, M2, M3, M4) and column lines (54, 56) to thereby form and XOR gate on said column lines (54, 56) and diode transistor (M7). The diode transistor is connected between transistors (M5, M6), ROW line (50) and MATCH line (52), such that during CAM matches the diode transistor allows charge to be siphoned from MATCH line ( 52) and during a write to said CAM cell allows charge to build up.