logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4683488 B1

PDFFull Text
Date of Patent:
Jul. 28, 1987

Filed:

Feb. 28, 1986

Latch-up resistant cmos structure for vlsi including retrograded wells

Applicant:
Inventors:

William W Lee, Fullerton, CA (US);

Kuang-Yeh Chang, Fountain Valley, CA (US);

Assignee:

Hughes Aircraft Company, Los Angeles, CA (US);

Attorneys:

Szabo; J. E.

Float; K. W.

Karambelas; A. W.

Primary Examiner:

Joseph E Clawson, Jr

Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 42 ; 357 2311 ; 357 38 ; 357 52 ; 357 56 ; 357 90 ;
Abstract

A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices. The CMOS structure includes trenches between the individual transistor devices, and highly doped field regions are formed in the bottom of the trenches. Each N- and P-well includes a retrograde impurity concentration profile and extends beneath adjacent trenches.

Find Patent Forward Citations

Lee, William. (1987). Latch-up resistant cmos structure for vlsi including retrograded wells (U.S. Patent No. 4683488). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4683488

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…