Low impedance package for integrated circuit die

Abstract

A low inductive impedance dual in-line package for an integrated circuit die incorporates a lead frame formed with a central opening without a die attach paddle. A ground plate forms the die attach plane spaced from and parallel with the lead frame. A dielectric layer is formed between the lead frame and ground plate. The lead frame is formed with a ground lead finger electrically coupled in parallel with the ground plate thereby providing a ground path through the ground plate with planar configuration to minimize inductive impedance to ground current and to minimize cross coupling between the electrically active lead fingers of the lead frame. In the preferred embodiment, the lead frame and ground plate are initially supported in a spaced parallel plane relationship by complementary spacing tab elements. During encapsulation, the encapsulation molding compound is introduced between the lead frame and ground plate to form the dielectric layer. A low impedance lead frame is also described in which the power lead finger and ground lead finger are at least 2.5 times wider than the signal lead finger for cooperating with the ground plane and for minimizing inductive reactance to power currents and ground currents. The package may be further stabilized by incorporating an internal decoupling capacitor. The invention is particularly applicable to dual in-line packages (DIP'S) and provides a method for extending DIP technology for high speed low inductance applications.