The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 1987

Filed:

Nov. 29, 1984
Applicant:
Inventors:

Robert R Doering, Plano, TX (US);

Michael P Duane, Houston, TX (US);

Gregory J Armstrong, Houston, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 29571 ; 29578 ; 148-15 ; 148187 ; 148D / ; 148D / ; 357 42 ; 357 91 ;
Abstract

A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.


Find Patent Forward Citations

Doering, Robert. (1987). High density cmos integrated circuit manufacturing process (U.S. Patent No. 4677739). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4677739

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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