The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 1987
Filed:
Jun. 06, 1986
Patricia C Elkins, Long Beach, CA (US);
Yau-Wai D Chan, Fullerton, CA (US);
Keh-Fei C Chi, Garden Grove, CA (US);
Karen A Reinhardt, Tustin, CA (US);
Rebecca Y Tang, Anaheim, CA (US);
Robert L Zwingman, Walnut, CA (US);
Rockwell International Corporation, El Segundo, CA (US);
Abstract
A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.