The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 1987

Filed:

Oct. 07, 1985
Applicant:
Inventors:

Martin P Lepselter, Summit, NJ (US);

Ashok K Sinha, New Providence, NJ (US);

Sheila Vaidya, New Providence, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 59 ; 357 15 ; 357 43 ; 357 34 ; 357 / ; 357 / ; 357-2 ;
Abstract

A resistive load element comprises a Schottky barrier metal layer formed on the top surface of a doped p-type polycrystalline silicon (polysilicon) plug contacting a surface n.sup.+ zone located in a semiconductor body at a major horizontal surface thereof. The Schottky barrier metal layer is advantageously essentially a metal compound, such as titanium nitride, which does not react with the polysilicon and which forms a Schottky barrier contact with the polysilicon top surface of the plug. The polysilicon plug extends vertically down to the n.sup.+ zone through an aperture in an insulating layer that coats the major surface of the semiconductor body. The top surface of the Schottky barrier layer is coated with another metal layer, such as aluminum, for interconnection purposes. A pair of such elements can be integrated as loads, for example, in a static random access memory ('flip-flop') cell.


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