The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1987
Filed:
May. 29, 1985
Bhimachar Venkatesh, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A high voltage isolation circuit for CMOS networks includes a N-channel MOS pass transistor for isolating a high voltage node from a low voltage node so as to prevent CMOS latch-up. There is provided a substrate of N-conductivity type and a P-conductivity region diffused in the substrate to form a PN junction. A supply potential is applied to the substrate. The pass transistor has a conduction path and a control electrode in which one end of the conduction path defines a first node for receiving thereat a first voltage, and the other end of the conduction path defines a second node for receiving thereat a second voltage. The first node is connected to the P-conductivity region. During a first mode of operation, the pass transistor is rendered more conductive so that the first node is coupled to the second node so that the second voltage follows the first voltage. During a second mode of operation, the pass transistor is rendered less conductive so that the second node is isolated from the first node so that the second voltage, which is allowed to be charged higher than the supply potential, is prevented from being applied to the P-conductivity region thereby avoiding latch-up.