Dynamic ram with reduced substrate noise and equal access and cycle time

Abstract

There is described a CMOS random access memory having memory access circuitry which substantially eliminates substrate noise caused by capacitive coupling of the bit lines to the substrate, and which allows the memory to have equal length access and cycle times. Access circuitry for each column of cells includes a pair of differential bit lines, at least one bit line equalization transistor, and a CMOS sense amp. The sense amp has two p-channel pull-up transistors, each having its source node connected to a common pull-up node, and two n-channel pull-down transistors, each having its source node connected to a common pull-down node. At the beginning of each memory access cycle the differential bit lines are equalized and the common pull-up and pull-down nodes are equalized. Then, substantially simultaneously, the common pull-up node is charged while the common pull-down node is discharged. By making the bit line charging and discharging activities simultaneous, the substrate noise normally generated by bit line to substrate capacitive coupling is virtually eliminated. Furthermore, since bit line precharge is performed at the beginning of each access cycle, rather than between access cycles, the access and cycle times of the memory are equal.