The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 1987
Filed:
Aug. 19, 1985
Nancy R Cservak, Wappingers Falls, NY (US);
Susan K Fribley, Beacon, NY (US);
George R Goth, Poughkeepsie, NY (US);
Mark A Takacs, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar polyimide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate. Next, by means of a thermal step, the blockout photoresist is caused to reflow to form a relatively thick photoresist layer over the high trench density regions and a thin photoresist layer over the low trench density regions, thereby exactly compensating for the non-planarity of the polyimide layer.