The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 1987
Filed:
Mar. 07, 1986
Applicant:
Inventors:
Thomas C Holloway, Dallas, TX (US);
Thomas E Tang, Dallas, TX (US);
Che-Chia Wei, Plano, TX (US);
Roger A Haken, Richardson, TX (US);
David A Bell, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
C23F / ; B44C / ; H01L / ; C03C / ;
U.S. Cl.
CPC ...
156643 ; 29571 ; 2957 / ; 29591 ; 156644 ; 156646 ; 156653 ; 156656 ; 1566591 ; 20419232 ; 252 791 ; 427 89 ;
Abstract
A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.
Quick Actions:
Holloway, Thomas. (1987). Process for patterning local interconnects (U.S. Patent No. 4657628). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4657628
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile