The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 1987

Filed:

May. 17, 1984
Applicant:
Inventors:

Thomas W MacElwee, Ottawa, CA;

Iain D Calder, Nepean, CA;

James J White, Ashton, CA;

Assignee:

Northern Telecom Limited, Montreal, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 29571 ; 2957 / ; 2957 / ; 2957 / ; 29578 ; 29580 ; 148-15 ; 148175 ; 148D / ; 148D / ; 156612 ; 357 237 ; 357 239 ; 357 42 ; 357 59 ;
Abstract

In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.


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