The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 1987
Filed:
Aug. 26, 1985
Robert E Kay, Newport Beach, CA (US);
Hakchill Chan, Corona del Mar, CA (US);
Fred Ju, Huntington Beach, CA (US);
Burton A Bray, Laguna Niguel, CA (US);
Ford Aerospace & Communications Corporation, Detroit, MI (US);
Abstract
A layer of HgCdTe (15) is epitaxially grown onto a CdTe substrate (5). A HgTe source (3) is spaced from the CdTe substrate (5) a distance of between 0.1 mm and 10 mm. The substrate (5) and source (3) are heated within a temperature range of between 500.degree. C. and 625.degree. C. for a processing step having a duration of between 5 minutes and 4 hours. During at least 5 minutes of this processing step, the substrate (5) is made to have a greater temperature than the source (3). Preferably the substrate (5) is never at a lower temperature than the source (3). The source (3) and substrate (5) are heated together in a thermally insulating, reusable ampoule (17). The CdTe substrate (5) is preferably a thin film epitaxially grown on a support (10) e.g., of sapphire or GaAs. When support (10) is not used, the CdTe substrate (5) is polished; and sublimation and solid state diffusion growth mechanisms are present in the growth of the HgCdTe (15). Means are disclosed for preventing contamination of the reactants during HgTe (3) synthesis and bulk CdTe wafer (5) polishing.