The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 1987
Filed:
Jul. 17, 1985
Applicant:
Inventor:
Walter R Curtice, Princeton Junction, NJ (US);
Assignee:
RCA Corporation, Princeton, NJ (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 16 ; 357 232 ; 357 233 ; 357 2311 ; 357 2312 ;
Abstract
A semiconductor structure GaInAs provides significantly low output capacitance in a digital integrated circuit, such as an inverter. A dopant density (N) within the range of 1.0.times.10.sup.16 cm.sup.-3 and 4.7.times.10.sup.16 cm.sup.-3 and an active layer thickness (a) within the range of 0.15 micrometer and 0.33 micrometer are selected in proper combination to provide a design criterion to provide good device performance with a significantly small propagation delay between the input and output terminals.
Curtice, Walter. (1987). Fast ternary (gainas) logic gate device (U.S. Patent No. 4639752). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4639752
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile